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| INTEL387 TM SX MATH COPROCESSOR Y New Automatic Power Management Low Power Consumption Typically 100 mA in Dynamic Mode and 4 mA in Idle Mode Socket Compatible with INTEL387 Family of Math CoProcessors Hardware and Software Compatible Supported by Over 2100 Commercial Software Packages 10% to 15% Performance Increase on Whetstone and Livermore Benchmarks Y Y Compatible with the Intel386 TM SX Microprocessor Extends CPU Instruction Set to Include Trigonometric Logarithmic and Exponential High Performance 80-Bit Internal Architecture Implements ANSI IEEE Standard 754-1985 for Binary Floating-Point Arithmetic Available in a 68-Pin PLCC Package See Intel Packaging Specification Order 231369 Y Y Y The INTEL387 TM SX Math CoProcessor is an extension to the Intel386 TM SX microprocessor architecture The combination of the INTEL387 TM SX with the Intel386 TM SX microprocessor dramatically increases the processing speed of computer application software that utilizes high performance floating-point operations An internal Power Management Unit enables the INTEL387 TM SX to perform these floating-point operations while maintaining very low power consumption for portable and desktop applications The internal Power Management Unit effectively reduces power consumption by 95% when the device is idle The INTEL387 TM SX Math CoProcessor is available in a 68-pin PLCC package and is manufactured on Intel's advanced 1 0 micron CHMOS IV technology 240225 - 22 Intel386 and INTEL387 are trademarks of Intel Corporation Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata January 1994 COPYRIGHT INTEL CORPORATION 1995 Order Number 240225-009 1 INTEL387 TM SX Math CoProcessor CONTENTS 1 0 PIN ASSIGNMENT 1 1 Pin Description Table 2 0 FUNCTIONAL DESCRIPTION 2 1 Feature List 2 2 Math CoProcessor Architecture 2 3 Power Management 2 3 1 Dynamic Mode 2 3 2 Idle Mode 2 4 Compatibility 2 5 Performance 3 0 PROGRAMMING INTERFACE 3 1 Instruction Set 3 1 1 Data Transfer Instructions 3 1 2 Arithmetic Instructions 3 1 3 Comparison Instructions 3 1 4 Transcendental Instructions 3 1 5 Load Constant Instructions 3 1 6 Processor Instructions 3 2 Register Set 3 2 1 Status Word (SW) Register 3 2 2 Control Word (CW) Register 3 2 3 Data Register 3 2 4 Tag Word (TW) Register 3 2 5 Instruction and Data Pointers 3 3 Data Types 3 4 Interrupt Description 3 5 Exception Handling 3 6 Initialization 3 7 Processing Modes 3 8 Programming Support PAGE 5 6 7 7 7 8 8 8 8 8 9 9 9 9 10 10 10 11 11 12 15 16 16 16 18 18 18 21 21 21 CONTENTS 4 0 HARDWARE SYSTEM INTERFACE 4 1 Signal Description 4 1 1 Intel386 CPU Clock 2 (CPUCLK2) 4 1 2 INTEL387 Math CoProcessor Clock 2 (NUMCLK2) 4 1 3 Clocking Mode (CKM) 4 1 4 System Reset (RESETIN) 4 1 5 Processor Request (PEREQ) 4 1 6 Busy Status (BUSY ) 4 1 7 Error Status (ERROR ) 4 1 8 Data Pins (D15-D0) 4 1 9 Write Read Bus Cycle (W R ) 4 1 10 Address Stobe (ADS ) 4 1 11 Bus Ready Input (READY ) 4 1 12 Ready Output (READYO ) 4 1 13 Status Enable (STEN) 4 1 14 Math CoProcessor Select 1 (NPS1 ) 4 1 15 Math CoProcessor Select 2 (NPS2) 4 1 16 Command (CMD0 ) 4 1 17 System Power (VCC) 4 1 18 System Ground (VSS) 4 2 System Configuration 4 3 Math CoProcessor Architecture 4 3 1 Bus Control Logic 4 3 2 Data Interface and Control Unit 4 3 3 Floating Point Unit 4 3 4 Power Management Unit PAGE 21 22 22 22 23 23 23 23 23 23 23 23 24 24 24 24 24 24 24 24 25 26 26 26 26 26 2 2 CONTENTS 4 4 Bus Cycles 4 4 1 INTEL387 SX Math CoProcessor Addressing 4 4 2 CPU Math CoProcessor Synchronization 4 4 3 Synchronous Asynchronous Modes 4 4 4 Automatic Bus Cycle Termination 5 0 BUS OPERATION 5 1 Non-pipelined Bus Cycles 5 1 1 Write Cycle 5 1 2 Read Cycle 5 2 Pipelined Bus Cycles 5 3 Mixed Bus Cycles 5 4 BUSY and PEREQ Timing Relationship 6 0 PACKAGE SPECIFICATIONS 6 1 Mechanical Specifications 6 2 Thermal Specifications PAGE 26 27 27 27 27 27 28 28 29 29 30 32 33 33 33 CONTENTS 7 0 ELECTRICAL CHARACTERISTICS 7 1 Absolute Maximum Ratings 7 2 D C Characteristics 7 3 A C Characteristics PAGE 33 33 34 35 41 A-1 A-1 A-1 A-2 8 0 INTEL387 SX MATH COPROCESSOR INSTRUCTION SET APPENDIX A INTEL387 SX MATH COPROCESSOR COMPATIBILITY A 1 8087 80287 Compatibility A 1 1 General Differences A 1 2 Exceptions APPENDIX B COMPATIBILITY BETWEEN THE 80287 AND 8087 MATH COPROCESSOR B-1 3 3 CONTENTS FIGURES Figure 1-1 PAGE CONTENTS Figure 7-2 CPUCLK2 NUMCLK2 Waveform and Measurement Points for Input Output Output Signals Input and I O Signals RESET Signal Float from STEN Other Parameters PAGE INTEL387 SX Math CoProcessor Pinout Figure 2-1 INTEL387 SX Math CoProcessor Block Diagram Figure 3-1 Intel 386 SX CPU and INTEL387 Math CoProcessor Register Set Figure 3-2 Status Word Figure 3-3 Control Word Figure 3-4 Tag Word Register Figure 3-5 Instruction and Data Pointer Image in Memory 32-Bit Protected Mode Format Figure 3-6 Instruction and Data Pointer Image in Memory 16-Bit Protected Mode Format Figure 3-7 Instruction and Data Pointer Image in Memory 32-Bit Real Mode Format Figure 3-8 Instruction and Data Pointer Image in Memory 16-Bit Real Mode Format Figure 4-1 Intel386 SX CPU and INTEL387 SX Math CoProcessor System Configuration Figure 5-1 Bus State Diagram Figure 5-2 Non-Pipelined Read and Write Cycles Figure 5-3 Fastest Transition to and from Pipelined Cycles Figure 5-4 Pipelined Cycles with Wait States Figure 5-5 BUSY and PEREQ Timing Relationship Figure 7-1a Typical Output Valid Delay vs Load Capacitance at Max Operating Temperature Figure 7-1b Typical Output Slew Time vs Load Capacitance at Max Operating Temperature Figure 7-1c Maximum ICC vs Frequency 5 38 38 39 39 40 40 7 11 12 15 16 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 TABLES Table 1-1 17 17 17 18 25 28 29 30 31 32 37 37 37 Pin Cross Reference Functional Grouping Table 3-1 Condition Code Interpretation Table 3-2 Condition Code Interpretation after FPREM and FPREM1 Instructions Table 3-3 Condition Code Resulting from Comparison Table 3-4 Condition Code Defining Operand Class Table 3-5 Mapping Condition Codes to Intel386 CPU Flag Bits Table 3-6 INTEL387 SX Math CoProcessor Data Type Representation in Memory Table 3-7 CPU Interrupt Vectors Reserve for Math CoProcessor Table 3-8 INTEL387 SX Math CoProcessor Exceptions Table 4-1 Pin Summary Table 4-2 Output Pin Status during Reset Table 4-3 Bus Cycle Definition Table 6-1 Thermal Resistances ( C Watt) iJC and iJA Table 6-2 Maximum TA at Various Airflows Table 7-1 D C Specifications Table 7-2a Timing Requirements of the Bus Interface Unit Table 7-2b Timing Requirements of the Execution Unit Table 7-2c Other AC Parameters Table 8-1 Instruction Formats 5 13 14 14 14 14 19 20 20 22 23 26 33 33 34 35 36 36 41 4 4 INTEL387 TM SX MATH COPROCESSOR include VCC and VSS planes for power distribution and all VCC and VSS pins must be connected to the appropriate plane NOTE Pins identified as N C should remain completely unconnected 10 PIN ASSIGNMENT The INTEL387 SX Math CoProcessor pinout as viewed from the top side of the component is shown in Figure 1-1 VCC and VSS (GND) connections must be made to multiple pins The circuit board should 240225 - 1 Figure 1-1 INTEL387 TM SX Math CoProcessor Pinout Functional Grouping 4 9 13 22 26 31 33 37 39 43 46 50 58 62 64 VSS 5 14 21 25 27 32 34 38 42 55 60 61 63 66 NC 1 10 17 18 52 65 67 68 Table 1-1 Pin Cross Reference BUSY PEREQ ERROR ADS CMD0 NPS1 NPS2 STEN WR READY READYO CKM CPUCLK2 NUMCLK2 RESETIN 36 56 35 47 48 44 45 40 41 49 57 59 54 53 51 D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 19 20 23 8 7 6 3 2 24 28 29 30 16 15 12 11 VCC 5 5 INTEL387 TM SX MATH COPROCESSOR 11 Pin Description Table The following table lists a brief description of each pin on the INTEL387 SX Math CoProcessor For a more complete description refer to Section 4 1 Signal Description The following definitions are used in these descriptions The signal is active LOW I O IO Input Signal Output Signal Input and Output Signal Type I O I I I IO O Name and Function ADDRESS STROBE indicates that the address and bus cycle definition is valid BUSY indicates that the Math CoProcessor is currently executing an instruction CLOCKING MODE is used to select synchronous or asynchronous clock modes COMMAND determines whether an opcode or operand are being sent to the Math CoProcessor During a read cycle it indicates which register group is being read CPU CLOCK input provides the timing for the bus interface unit and the execution unit in synchronous mode DATA BUS is used to transfer instructions and data between the Math CoProcessor and CPU ERROR signals that an unmasked exception has occurred NO CONNECT should always remain unconnected Connection of a N C pin may cause the Math CoProcessor to malfunction or be incompatible with future steppings I I I O I O I I NPX SELECT 1 is used to select the Math CoProcessor NPX SELECT 2 is used to select the Math CoProcessor NUMERICS CLOCK is used in asynchronous mode to drive the Floating Point Execution Unit PROCESSOR EXTENSION REQUEST signals the CPU that the Math CoProcessor is ready for data transfer to from its FIFO READY indicates that the bus cycle is being terminated READY OUT signals the CPU that the Math CoProcessor is terminating the bus cycle SYSTEM RESET terminates any operation in progress and forces the Math CoProcessor to enter a dormant state STATUS ENABLE serves as a master chip select for the Math CoProcessor When inactive this pin forces all outputs and bi-directional pins into a floating state WRITE READ indicates whether the CPU bus cycle in progress is a read or a write cycle SYSTEM POWER provides the a 5V nominal D C supply input SYSTEM GROUND provides the 0V connection from which all inputs and outputs are measured Symbol ADS BUSY CKM CMD0 CPUCLK2 D15-D0 ERROR NC NPS1 NPS2 NUMCLK2 PEREQ READY READYO RESETIN STEN WR VCC VSS I I I 6 6 INTEL387 TM SX MATH COPROCESSOR 20 FUNCTIONAL DESCRIPTION Expands Intel386 SX CPU data types to include 32-bit 64-bit and 80-bit Floating Point 32-bit and 64-bit Integers and 18 Digit BCD Operands The INTEL387 SX Math CoProcessor is designed to support the Intel386 SX Microprocessor and effectively extend the CPU architecture by providing fast execution of arithmetic instructions and transcendental functions This component contains internal power management circuitry for reduced active power dissipation and an automatic idle mode Directly extends the Intel386 SX CPU Instruction Set to trigonometric logarithmic exponential and arithmetic functions for all data types Operates independently of Real Protected and Virtual-86 Modes of the Intel386 SX Microprocessors Fully compatible with the INTEL387 SL Mobile and 2 1 Feature List New power saving design provides low power dissipation in active and idle modes DX Math CoProcessors Implements all INTEL387 Math CoProcessor architectural enhancements over 8087 and 80287 Implements ANSI IEEE Standard 754-1985 for binary floating point arithmetic Higher Performance 10%-25% higher benchmark performance than the original INTEL387 SX Math CoProcessor Upward Object Code compatible from 8087 and 80287 High Performance 84-bit Internal Architecture Eight 80-bit Numeric Registers usable as individually addressable general registers or as a register stack 2 2 Math CoProcessor Architecture As shown in Figure 2-1 the INTEL387 SX Math CoProcessor is internally divided into four sections the Bus Control Logic the Data Interface and Control Logic the Floating Point Unit and the Power Management Unit The Bus Control Logic is responsible for the CPU bus tracking and interface The Data Interface and Control Unit latches data and decodes instructions The Floating Point Unit executes the mathematical instructions The Power Management Unit is new to the INTEL387 family and is the nucleus Full-range transcendental operations for SINE COSINE TANGENT ARCTANGENT and LOGARITHM Programmable rounding modes and notification of rounding effects Exception reporting either by software polling or hardware interrupts Fully compatible with the SX Microprocessors 240225 - 2 Figure 2-1 INTEL387 TM SX Math CoProcessor Block Diagram 7 7 INTEL387 TM SX MATH COPROCESSOR of the static architecture It is responsible for shutting down idle sections of the device to save power Microprocessor Math CoProcessor Interface The Intel386 CPU interprets the pattern 11011B in most significant five bits of an instruction as an opcode intended for a math coprocessor Instructions thus marked are called ESCAPE or ESC instructions Upon decoding the instruction as an ESC instruction the Intel386 CPU transfers the opcode to the math coprocessor through an I O write cycle at a dedicated address (8000F8H) outside the normal programmed I O address range The math coprocessor has dedicated output signals for controlling the data transfer and notifying the CPU if the Math CoProcessor is busy or that a floating point error has occurred Math CoProcessor accepts the instruction and ramps the internal core within one clock so there is no impact to performance or throughput In idle mode the INTEL387 SX Math CoProcessor draws typically 4 mA of current and reduces case temperature to near ambient NOTE In asynchronous clock mode (CKM e 0) the internal idle mode is disabled 2 4 Compatibility The INTEL387 SX Math CoProcessor is compatible with the INTEL387 SL Mobile Math CoProcessor Due to the increased performance and internal pipelining effects diagnostic programs should never use instruction execution time for test purposes 2 3 Power Management The INTEL387 SX Math CoProcessor offers two modes of power management dynamic and idle 2 3 1 DYNAMIC MODE 2 5 Performance The increased performance of floating point calculations can be attributed to the 84-bit architecture and floating point processor For the CPU to execute floating point calculations requires very long software emulation methods with reduced resolution and accuracy The performance of the INTEL387 SX Math CoProcessor has been further enhanced through improvements in the internal microcode and through internal architectural changes These refinements will increase Whetstone benchmarks by approximately 10% to 25% over the original INTEL387 SX Math CoProcessor Real performance however should be measured with application software Depending upon software coding system overhead and percentage of floating point instructions performance can vary significantly Dynamic Mode is when the device is executing an instruction Using Intel's CHMOS IV technology the INTEL387 SX Math CoProcessor draws considerably less power than its predecessor The active power supply current is reduced to approximately 100 mA at 20 MHz and provides low case temperatures 2 3 2 IDLE MODE When an instruction is not being executed the INTEL387 SX Math CoProcessor will automatically change to Idle Mode Three clocks after completion of the previous instruction the internal power manager shuts down the floating point execution unit and all non-essential circuitry Only portions of the Bus Interface Unit remain active to monitor the CPU bus activity and to accept the next instruction when it is transferred When the CPU transfers the next instruction to the Math CoProcessor the INTEL387 SX 8 8 INTEL387 TM SX MATH COPROCESSOR Integer Transfers Load (convert from) Integer (word short long) FIST Store (convert to) Integer (word short) FISTP Store (convert to) Integer and pop (word short long) Packed Decimal Transfers FBLD Load (convert from) packed decimal FBSTP Store packed decimal and pop 3 1 2 ARITHMETIC INSTRUCTIONS This class of instructions provide variations on the basic add subtract multiply and divide operations and a number of other basic arithmetic operations Operands may reside in registers or one operand may reside in memory Addition FADD FADDP FIADD The Intel386 CPU interprets the pattern 11011B in most significant five bits of an instruction as an opcode intended for a math coprocessor Instructions thus marked are called ESCAPE or ESC instruction The typical Math CoProcessor instruction accepts one or two operands and produces one or sometimes two results In two-operand instructions one operand is the contents of the Math CoProcessor register while the other may be a memory location The operands of some instructions are predefined for example FSQRT always takes the square root of the number in the top stack element The INTEL387 SX Math CoProcessor instruction set can be divided into six groups The following sections gives a brief description of each instruction Section 8 0 defines the instruction format and byte fields Further details can be obtained from the INTEL387 User's Manual Programmer's Reference Order 231917 3 1 1 DATA TRANSFER INSTRUCTIONS The class includes the operations that load store and convert operands of any support data types Real Transfers FLD Load Real (single double extended) FST Store Real (single double) FSTP Store Real and pop (single double extended) FXCH Exchange registers 9 9 30 PROGRAMMING INTERFACE The INTEL387 SX Math CoProcessor effectively extends to an Intel386 Microprocessor system additional instructions registers data types and interrupts specifically designed to facilitate high-speed floating point processing All communication between the CPU and the Math CoProcessor is transparent to applications software The CPU automatically controls the Math CoProcessor whenever a numerics instruction is executed All physical memory and virtual memory of the CPU are available for storage of the instructions and operands of programs that use the Math CoProcessor All memory addressing modes including use of displacement base register index register and scaling are available for addressing numerical operands The INTEL387 SX Math CoProcessor is software compatible with the INTEL387 DX Math CoProcessors and supports all applications written for the Intel386 CPU and INTEL387 Math CoProcessors FILD 3 1 Instruction Set Add Real Add Real and pop Add Integer Subtraction FSUB FSUBP Subtract Real Subtract Real and pop FISUB Subtract Integer FSUBR Subtract Real reversed FSUBRP Subtract Real reversed and pop FISUBR Subtract Integer reversed Multiplication FMUL Multiply Real FMULP Multiply Real and pop FIMUL Division FDIV FDIVP FIDIV FDIVR FDIVRP FIDIVR Multiply Integer Divide Divide Divide Divide Divide Divide Real Real and pop Integer Real reversed Real reversed and pop Integer reversed INTEL387 TM SX MATH COPROCESSOR Other Operations FSQRT FSCALE FPREM Square Root Scale Partial Remainder 3 1 4 TRANSCENDENTAL INSTRUCTIONS This group of the INTEL387 operations includes trigonometric inverse trigonometric logarithmic and exponential functions The transcendental operate on the top one or two stack elements and they return their results to the stack The trigonometric operations assume their arguments are expressed in radians The logarithmic and exponential operations work in base 2 FSIN Sine FCOS Cosine FSINCOS Sine and cosine FPTAN FPATAN F2XM1 FYL2X Tangent Arctangent of ST(1) ST 2x -1 Y log2X log2(X a 1) FPREM1 IEEE standard partial remainder FRNDINT Round to Integer FXTRACT Extract Exponent and Significand FABS Absolute Value FCHS Change sign 3 1 3 COMPARISON INSTRUCTION Instructions of this class allow comparison of numbers of all supported real and integer data types Each of these instructions analyzes the top stack element often in relationship to another operand and reports the result as a condition code in the status word FCOM Compare Real FCOMP FCOMPP FUCOM Compare Real and pop Compare Real and pop twice Unordered compare Real FYL2XP1 Y 3 1 5 LOAD CONSTANT INSTRUCTIONS Each of these instructions loads (pushes) a commonly used constant onto the stack The constants have extended real values nearest to the infinitely precise numbers The only error that can be generated is an Invalid Exception if a stack overflow occurs FLDZ FLD1 FLDPI FLDL2T FLDL2E FLDLG2 FLDLN2 Load a 0 0 Load Load Load Load Load Load a1 0 FUCOMP Unordered compare Real and pop FUCOMPP Unordered compare Real and pop twice FICOM Compare Integer FICOMP Compare Integer and pop FTST FXAM Test Examine q log2 10 log2e log102 loge2 10 10 INTEL387 TM SX MATH COPROCESSOR FRSTOR FINCSTP FFREE FNOP FWAIT Restore State Increment Stack pointer Free Register No Operation Report Math CoProcessor Error 3 1 6 PROCESSOR INSTRUCTIONS (ADMINISTRATIVE) FINIT FLDCW FSTCW FLDCW FSTSW Initialize Math CoProcessor Load Control Word Store Control Word Load Status Word Store Status Word FDECSTP Decrement Stack pointer FSTSW AX Store Status Word to AX register FCLEX Clear Exceptions FSTENV FLDENV FSAVE Store Environment Load Environment Save State 3 2 Register Set Figure 3-1 shows the INTEL387 SX Math CoProcessor register set When a Math CoProcessor is present in a system programmers may use these registers in addition to the registers normally available on the CPU i386 TM Microprocessor Registers GENERAL REGISTERS 31 16 15 0 EAX AH EBX BH ECX CH EDX ESI EDI EBP ESP DX DH SI 31 DI BP SP EIP EFLAGS 0 DL CX CL BX BL AX AL SEGMENT REGISTERS 15 0 CS SS DS ES FS GS l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l i387 TM Math CoProcessor Data Registers Tag Field 10 79 R0 R1 R2 R3 R4 R5 R6 R7 15 Sign 78 64 63 Significand 0 Exponent 0 Status Register Tag Word 47 Instruction Pointer (in CPU) Data Pointer (in CPU) 0 Control Register Figure 3-1 Intel386 TM CPU and INTEL387 TM Math CoProcessor Register Set 11 11 INTEL387 TM SX MATH COPROCESSOR Bit 7 is the error summary (ES) status bit This bit is set if any unmasked exception bit is set it is clear otherwise If this bit is set the ERROR signal is asserted Bit 6 is the stack flag (SF) This bit is used to distinguish invalid operations due to stack overflow or underflow from other kinds of invalid operations When SF is set bit 9 (C1) distinguishes between stack overflow (C1 e 1) or underflow (C1 e 0) Bit 5 - 0 are the six exception flags of the status word and are set to indicate that during an instruction execution the Math CoProcessor has detected one of six possible exception conditions since these status bits were last cleared or reset Section 3 5 entitled Exception Handling explains how they are set and used The exception flags are ``sticky'' bits and can only be cleared by the instructions FINIT FCLEX FLDENV FSAVE and FRSTOR Note that when a new value is loaded into the status word by the FLDENV or FRSTOR instruction the value of ES (bit 7) and B (bit 15) are not derived from the values loaded from memory but rather are dependent upon the values of the exception flags (bits 5 - 0) in the status word and their corresponding masks in the control word If ES is set in such a case the ERROR output of the Math CoProcessor is activated immediately 3 2 1 STATUS WORD (SW) REGISTER The 16-bit status word (in the status register) shown in Figure 3-2 reflects the overall state of the Math CoProcessor It can be read and inspected by programs using the FSTSW memory or FSTSW AX instructions Bit 15 the Busy bit (B) is included for 8087 compatibility only It always has the same value as the Error Summary bit (ES bit 7 of status word) it does not indicate the status of the BUSY output of the Math CoProcessor Bits 13-11 (TOP) serves as the pointer to the Math CoProcessor data register that is the current Top-OfStack The significance of the stack top is described in Section 3 2 5 Data Registers The four numeric condition code bits (C3 -C0 Bit 14 10-8) are similar to the flags in a CPU instructions that perform arithmetic operations update these bits to reflect the outcome The effects of the instructions on the condition code are summarized in Tables 3-1 through 3-4 These condition code bits are used principally for conditional branching The FSTSW AX instructions stores the Math CoProcessor status word directly to the CPU AX register allowing the condition codes to be inspected efficiently by Intel386 CPU code The Intel386 CPU SAHF instruction can copy C3 -C0 directly to the flag bits to simplify conditional branching Table 3-5 shows the mapping of these bits to the Intel386 CPU flag bits 240225 - 3 ES is set if any unmasked exception bit is set cleared otherwise See Table 2-2 for interpretation of condition code TOP values 000 e Register 0 is Top of Stack 001 e Register 1 is Top of Stack 111 e Register 7 is Top of Stack For definitions of exceptions refer to the section entitled ``Exception Handling'' Figure 3-2 Status Word 12 12 INTEL387 TM SX MATH COPROCESSOR Table 3-1 Condition Code Interpretation Instruction FPREM FPREM1 (see Table 3-2) Q2 FCOM FCOMP FCOMPP FTST FUCOM FUCOMP FUCOMPP FICOM FICOMP FXAM FCHS FABS FXCH FINCSTP FDECSTP Constant loads FXTRACT FLD FILD FBLD FSTP (ext real) FIST FBSTP FRNDINT FST FSTP FADD FMUL FDIV FDIVR FSUB FSUBR FSCALE FSQRT FPATAN F2XM1 FYL2X FYL2XP1 FPTAN FSIN FCOS FSINCOS C0 (S) C3 (Z) Three least significant bits of quotient Q0 C1 (A) C2 (C) Reduction 0 e complete 1 e incomplete Q1 or O U Result of comparison (see Table 3-3) Zero or O U Operand is not comparable (Table 3-3) Operand class (Table 3-4) Operand class (see Table 3-4) Sign or O U UNDEFINED Zero or O U UNDEFINED UNDEFINED Roundup or O U UNDEFINED UNDEFINED Roundup or O U undefined if C2 e 1 Reduction 0 e complete 1 e incomplete FLDENV FRSTOR FLDCW FSTENV FSTCW FSTSW FCLEX FINIT FSAVE OU Reduction Each bit loaded from memory UNDEFINED Roundup UNDEFINED When both IE and SF bits of status word are set indicating a stack exception this bit distinguishes between stack overflow (C1 e 1) and underflow (C1 e 0) If FPREM or FPREM1 produces a remainder that is less than the modulus reduction is complete When reduction is incomplete the value at the top of the stack is a partial remainder which can be used as input to further reduction For FPTAN FSIN FCOS and FSINCOS the reduction bit is set if the operand at the top of the stack is too large In this case the original operand remains at the top of the stack When the PE bit of the status word is set this bit indicates whether the last rounding in the instruction was upward Do not rely on finding any specific value in these bits 13 13 INTEL387 TM SX MATH COPROCESSOR Table 3-2 Condition Code Interpretation after FPREM and FPREM1 Instructions Condition Code C2 1 C3 X Q1 0 0 1 1 0 0 1 1 C1 X Q0 0 1 0 1 0 1 0 1 C0 X Q2 0 0 0 0 1 1 1 1 Q MOD8 0 1 2 3 4 5 6 7 Incomplete Reduction further interation required for complete reduction Interpretation after FPREM and FPREM1 0 Complete Reduction C0 C3 C1 contain three least significant bits of quotient Table 3-3 Condition Code Resulting from Comparison Order TOP l Operand TOP k Operand TOP e Operand Unordered C3 0 0 1 1 C2 0 0 0 1 C0 0 1 0 1 Table 3-4 Condition Code Defining Operand Class C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 Value at TOP a Unsupported a NaN b Unsupported b NaN a Normal a Infinity b Normal b Infinity a0 a Empty b0 b Empty a Denormal b Denormal Table 3-5 Mapping Condition Codes to Intel386 TM CPU Flag Bits 240225 - 4 14 14 INTEL387 TM SX MATH COPROCESSOR 3 2 2 CONTROL WORD (CW) REGISTER The Math CoProcessor provides the programmer with several processing options that are selected by loading a control word from memory into the control register Figure 3-3 show the format and encoding of fields in the control word The low-order byte of the control word register is used to configure the exception masking Bits 5 - 0 of the control word contain individual masks for each of the six exceptions that the Math CoProcessor recognizes See Section 3 5 Exception Handling for further explanation on the exception control and definition The high-order byte of the control word is used to configure the Math CoProcessor operating mode including precision rounding and infinity control The precision control (PC) field (bits 9 - 8) can be used to set the Math CoProcessor internal operating precision of the significand at less than the default of 64 bits (extended precision) This can be useful in providing compatibility with early generation arithmetic processors of smaller precision PC affects only the instructions FADD FSUB(R) FMUL FDIV(R) and FSQRT For all other instructions either the precision is determined by the opcode or extended precision is used The ``infinity control bit'' (bit 12) is not meaningful to the INTEL387 SX Math CoProcessor and programs must ignore its value To maintain compatibility with the 8087 and 80287 (non-387 core) this bit can be programmed however regardless of its value the INTEL387 SX Math CoProcessor always treats infinity in the affine sense ( b % k a % ) This bit is initialized to zero both after a hardware reset and after FINIT instruction All other bits are reserved and should not be programmed to assure compatibility with future processors The rounding control (RC) field (bits 11-10) provide for directed rounding and true chop as well as the unbiased round to nearest even mode specified in the IEEE standard Rounding control affects only those instructions that perform rounding at the end of the operation (and thus can generate a precision exception) namely FST FSTP FIST all arithmetic instructions (except FPREM FPREM1 FXTRACT FABS and FCHS) and all transcendental instructions 240225 - 5 Precision Control 00 24 bits (single precision) 01 (reserved) 10 53 bits (double precision) 11 64 bits (extended precision) Rounding Control 00 Round to nearest or even 01 Round down (toward b% ) 10 Round up (toward a % ) 11 Chop (truncate toward zero) Figure 3-3 Control Word 15 15 INTEL387 TM SX MATH COPROCESSOR pal function of the tag word is to optimize the Math CoProcessor's performance and stack handling by making it possible to distinguish between empty and non-empty register locations It also enables exception handlers to identify special values (e g NaNs or denormals) in the contents of a stack location without the need to perform complex decoding of the actual data 3 2 5 INSTRUCTION AND DATA POINTERS Because the Math CoProcessor operates in parallel with the CPU any exceptions detected by the Math CoProcessor may be reported after the CPU has executed the ESC instruction which caused it To allow identification of the numeric instruction which caused the exception the Intel386 Microprocessor contains registers that aid in diagnosis These registers supply the address of the failing instruction and the address of its numeric memory operand (if appropriate) The instruction and data pointers are provided for user-written exception handlers These registers are located in the CPU but appear to be located in the Math CoProcessor because they are accessed by the ESC instructions FLDENV FSTENV FSAVE and FRSTOR which transfer the values between the registers and memory Whenever the CPU executes a new ESC instruction (except administrative instructions) it saves the address of the instruction (including any prefixes that may be present) the address of the operand (if present) and the opcode The instruction and data pointers appear in one of four formats depending on the operating mode of the CPU (protected mode or real-address mode) and depending on the operand size attribute in effect (32-bit operand or 16-bit operand) (See Figures 3-5 3-6 3-7 and 3-8 ) Note that the value of the data pointer is undefined if the prior ESC instruction did not have a memory operand 3 2 3 DATA REGISTER INTEL387 SX Math CoProcessor data register set consists of eight registers (R0-R7) which are treated as both a stack and a general register file Each of these data registers in the Math CoProcessor is 80 bits wide and is divided into fields corresponding to the Math CoProcessor's extended-precision real data type which is used for internal calculations The Math CoProcessor register set can be accessed either as a stack with instructions operating on the top one or two stack elements or as individually addressable registers The TOP field in the status word identifies the current top-of-stack register A ``push'' operation decrements TOP by one and loads a value into the new top register A ``store and pop'' operation stores the value from the current top register into memory and then increments TOP by one The Math CoProcessor register stack grows ``down'' toward lower-addressed registers Most of the INTEL387 SX Math CoProcessor operations use the register stack as the operand(s) and or as a place to store the result Instructions may address the data register either implicitly or explicitly Many instructions operate on the register at the top of the stack These instructions implicitly address the register at which TOP points Other instructions allow the programmer to explicitly specify which register to use Explicit register addressing is also relative to TOP (where ST denotes the current stack top and ST(i) refers to the i'th register from the ST in the stack so the real register address in computed as ST a i) 3 2 4 TAG WORD (TW) REGISTER The tag word marks the content of each numeric data register as Figure 3-4 shows Each two-bit tag represents one of the eight data register The princi- 15 TAG (7) TAG (6) TAG (5) TAG (4) TAG (3) TAG (2) TAG (1) 0 TAG (0) NOTE The index i of tag(i) is not top-relative A program typically uses the ``top'' field of Status Word to determine which tag(i) field refers to logical top of stack TAG VALUES 00 e Valid 01 e Zero 10 e QNaN SNaN Infinity Denormal and Unsupported Formats 11 e Empty Figure 3-4 Tag Word Register 16 16 INTEL387 TM SX MATH COPROCESSOR 32-BIT PROTECTED MODE FORMAT 31 23 RESERVED RESERVED RESERVED IP OFFSET 00000 OPCODE 10 0 DATA OPERAND OFFSET RESERVED OPERAND SELECTOR CS SELECTOR 15 7 CONTROL WORD STATUS WORD TAG WORD 0 0 4 8 C 10 14 18 Figure 3-5 Instruction and Data Pointer Image in Memory 32-Bit Protected-Mode Format 16-BIT PROTECTED MODE FORMAT 7 CONTROL WORD STATUS WORD TAG WORD IP OFFSET CS SELECTOR OPERAND OFFSET OPERAND SELECTOR 15 0 0 2 4 6 8 A C Figure 3-6 Instruction and Data Pointer Image in Memory 16-Bit Protected-Mode Format 32-BIT REAL-ADDRESS MODE FORMAT 15 31 23 RESERVED RESERVED RESERVED RESERVED 0000 7 CONTROL WORD STATUS WORD TAG WORD 0 0 4 8 C 10 14 18 INSTRUCTION POINTER 15 0 0 OPCODE 10 0 INSTRUCTION POINTER 31 16 RESERVED OPERAND POINTER 15 0 0000 00000000 0000 OPERAND POINTER 31 16 Figure 3-7 Instruction and Data Pointer Image in Memory 32-Bit Real-Mode Format 17 17 INTEL387 TM SX MATH COPROCESSOR 16-BIT REAL-ADDRESS MODE AND VIRTUAL 8086 MODE FORMAT 15 7 CONTROL WORD STATUS WORD TAG WORD INSTRUCTION POINTER 15 0 IP19 16 0 OPCODE 10 0 0 0 2 4 6 8 A 0 0 C OPERAND POINTER 15 0 DP 19 16 0000000000 Figure 3-8 Instruction and Data Pointer Image in Memory 16-Bit Real-Mode Format 3 3 Data Types Table 3-6 lists the seven data types that the Math CoProcessor supports and presents the format for each type Operands are stored in memory with the least significant digit at the lowest memory address Programs retrieve these values by generating the lowest address For maximum system performance all operands should start at physical-memory addresses that correspond to the word size of the CPU operands may begin at any other addresses but will require extra memory cycles to access the entire operand The data type formats can be divided into three classes binary integer decimal integer and binary real These formats however exist in memory only Internally the Math CoProcessor holds all numbers in the extended-precision real format Instructions that load operands from memory automatically convert operands represented in memory as 16 32 or 64-bit integers 32 or 64-bit floating point numbers or 18 digit packed BCD numbers into extended-precision real format Instructions that store operands in memory perform the inverse type conversion In addition to the typical real and integer data values the INTEL387 SX Math CoProcessor data formats encompass encodings for a variety of special values These special values have significance and can express relevant information about the computations or operations that produced them The various types of special values are denormal real numbers zeros positive and negative infinity NaNs (Not-a-Number) Indefinite and unsupported formats For further information on data types and formats see the INTEL387 Programmer's Reference Manual 3 4 Interrupt Description CPU interrupts are used to report errors or exceptional conditions while executing numeric programs in either real or protected mode Table 3-7 shows these interrupts and their functions 3 5 Exception Handling The Math CoProcessor detects six different exception conditions that occur during instruction execution Table 3-8 lists the exception conditions in order of precedence showing for each the cause and the default action taken by the Math CoProcessor if the exception is masked by its corresponding mask bit in the control word Any exception that is not masked by the control word sets the corresponding exception flag of the status word sets the ES bit of the status word and asserts the ERROR signal When the CPU attempts to execute another ESC instruction or WAIT exception 16 occurs The exception condition must be resolved via an interrupt service routine The return address pushed onto the CPU stack upon entry to the service routine does not necessarily point to the failing instruction nor to the following instruction The CPU saves the address of the floating-point instruction that caused the exception and the address of any memory operand required by that instruction 18 18 INTEL387 TM SX MATH COPROCESSOR Table 3-6 INTEL387 TM SX Math CoProcessor Data Type Representation in Memory 240225 - 23 NOTES 1 S e Sign bit (0 e positive 1 e negative) 2 dn e Decimal digit (two per byte) 3 X e Bits have no significance Math CoProcessor ignores when loading zeros when storing 4 U e Position of implicit binary point 5 I e Integer bit of significand stored in temporary real implicit in single and double precision 6 Exponent Bias (normalized values) Single 127 (7FH) Double 1023 (3FFH) Extended REal 16383 (3FFFH) 7 Packed BCD (b1)S (D17 D0) 8 Real ( b1)S (2E-BIAS) (F0 F1 ) 19 19 INTEL387 TM SX MATH COPROCESSOR Table 3-7 CPU Interrupt Vectors Reserved for Math CoProcessor Interrupt Number 7 Cause of Interrupt An ESC instruction was encountered when EM or TS of CPU control register zero (CR0) was set EM e 1 indicates that software emulation of the instruction is required When TS is set either an ESC or WAIT instruction causes interrupt 7 This indicates that the current Math CoProcessor context may not belong to the current task In a protected-mode system an operand of a coprocessor instruction wrapped around an addressing limit (0FFFFH for expand-up segments zero for expand-down segments) and spanned inaccessible addresses(1) The failing numerics instruction is not restartable The address of the failing numerics instruction and data operand may be lost an FSTENV does not return reliable addresses The segment overrun exception should be handled by executing an FNINIT instruction (i e an FINIT without a preceding WAIT) The exception can be avoided by never allowing numerics operands to cross the end of a segment In a protected-mode system the first word of a numeric operand is not entirely within the limit of its segment The return address pushed onto the stack of the exception handler points at the ESC instruction that caused the exception including any prefixes The Math CoProcessor has not executed this instruction the instruction pointer and data pointer register refer to a previous correctly executed instruction The previous numerics instruction caused an unmasked exception The address of the faulty instruction and the address of its operand are stored in the instruction pointer and data pointer registers Only ESC and WAIT instructions can cause this interrupt The CPU return address pushed onto the stack of the exception handler points to a WAIT or ESC instruction (including prefixes) This instruction can be restarted after clearing the exception condition in the Math CoProcessor FNINIT FNCLEX FNSTSW FNSTENV and FNSAVE cannot cause this interrupt 9 13 16 NOTE 1 An operand may wrap around an addressing limit when the segment limit is near an addressing limit and the operand is near the largest valid address in the segment Because of the wrap-around the beginning and ending addresses of such an operand will be at opposite ends of the segment There are two ways that such an operand may also span inaccessible addresses 1) if the segment limit is not equal to the addressing limit (e g addressing limit is FFFFH and segment limit is FFFDH) the operand will span addresses that are not within the segment (e g an 8-byte operand that starts at valid offset FFFCH will span addresses FFFC-FFFFH and 0000-0003H however addresses FFFEH and FFFFH are not valid because they exceed the limit) 2) if the operand begins and ends in present and accessible segments but intermediate bytes of the operand fall in a not-present page or in a segment or page to which the procedure does not have access rights Table 3-8 INTEL387 TM SX Math CoProcessor Exceptions Exception Invalid Operation Denormalized Operand Zero Divisor Overflow Underflow Cause Operation on a signalling NaN unsupported format indeterminate for (0- % 0 0 ( a % ) a ( b % ) etc ) or stack overflow underflow (SF is also set) At least one of the operands is denormalized i e it has the smallest exponent but a nonzero significand The divisor is zero while the dividend is a noninfinite nonzero number The result is too large in magnitude to fit in the specified format The true result is nonzero but too small to be represented in the specified format and if underflow exception is masked denormalization causes the loss of accuracy The true result is not exactly representable in the specified format (e g 1 3) the result is rounded according to the rounding mode Default Action (if exception is masked) Result is a quiet NaN integer indefinite or BCD indefinte Normal processing continues Result is % Result is largest finite value or % Result is denormalized or zero Normal processing continues Inexact Result (Precision) 20 20 INTEL387 TM SX MATH COPROCESSOR tions and values passed to it by the CPU and therefore is not sensitive to the processing mode of the CPU The real-address mode and virtual-8086 mode the INTEL387 SX Math CoProcessor is completely upward compatible with software for the 8086 8087 and 80286 80287 real-address mode systems In protected mode the INTEL387 SX Math CoProcessor is completely upward compatible with software for the 80286 80287 protected mode system The only differences of operation that may appear when 8086 8087 programs are ported to the protected mode (not using virtual-8086 mode) is in the format of operands for the administrative instructions FLDENV FSTENV FRSTOR and FSAVE 3 6 Initialization After FNINIT or RESET the control word contains the value 037FH (all exceptions masked precision control 64 bits rounding to nearest) the same values as in an Intel287 after RESET For compatibility with the 8087 and Intel287 the bit that used to indicate infinity control (bit 12) is set to zero however regardless of its setting infinity is treated in the affine sense After FNINIT or RESET the status word is initialized as follows All exceptions are set to zero Stack TOP is zero so that after the first push the stack top will be register seven (111B) The condition code C3 -C0 is undefined The B-bit is zero The tag word contains FFFFH (all stack locations are empty) The Intel386 Microprocessor and INTEL387 Math CoProcessor initialization software must execute a FNINIT instruction (i e FINIT without a preceding WAIT) after RESET The FNINIT is not strictly required for the Intel386 software but Intel recommends its use to help ensure upware compatibility with other processors After a hardware RESET the ERROR output is asserted to indicate that an INTEL387 Math CoProcessor is present To accomplish this the IE (Invalid Exception) and ES (Error Summary) bits of the status word are set and the IM bit (Invalid Exception Mask) in the control word is cleared After FNINIT the status word and the control word have the same values as in an Intel287 Math CoProcessor after RESET 3 8 Programming Support Using the INTEL387 SX Math CoProcessor requires no special programming tools because all new instructions and data types are directly supported by the assembler and compilers for high-level languages All Intel386 Microprocessor development tools that support INTEL387 Math CoProcessor programs can also be used to develop software for the Intel386 SX Microprocessors and INTEL387 SX Math CoProcessors All 8086 8088 development tools that support the 8087 can also be used to develop software for the CPU and Math CoProcessor in realaddress mode or virtual-8086 mode All 80286 development tools that support the Intel287 Math CoProcessor can also be used to develop software for the Intel386 CPU and INTEL387 Math CoProcessor 3 7 Processing Modes The INTEL387 SX Math CoProcessor works the same whether the CPU is executing in real-addressing mode protected mode or virtual-8086 mode All references to memory for numerics data or status information are performed by the CPU and therefore obey the memory-management and protection rules of the CPU mode currently in effect The INTEL387 SX Math CoProcessor merely operates on instruc- 40 HARDWARE SYSTEM INTERFACE In the following description of hardware interface symbol at the end of a signal name indicates the that the active or asserted state occurs when the signal is at a low voltage When no is present after the signal name the signal is asserted when at the high voltage level 21 21 INTEL387 TM SX MATH COPROCESSOR also clocks the data interface and control unit and the floating point unit of the Math CoProcessor This pin requires CMOS-level input The signal on this pin is divided by two to produce the internal clock signal CLK 4 1 2 INTEL387 MATH COPROCESSOR CLOCK 2 (NUMCLK2) When CKM e 0 (asynchronous mode) this pin provides the clock for the data interface and control unit and the floating point unit of the Math CoProcessor In this case the ratio of the frequency of NUMCLK2 to the frequency of CPUCLK2 must lie within the range 10 16 to 14 10 and the maximum frequency must not exceed the device specifications When CKM e 1 (synchronous mode) signals on this pin are ignored CPUCLK2 is used instead for the data interface and control unit and the floating point unit This pin requires CMOS level input and should be tied low if not used 4 1 Signal Description In the following signal descriptions the INTEL387 SX Math CoProcessor pins are grouped by function as shown by Table 4-1 Table 4-1 lists every pin by its identifier gives a brief description and lists some of its characteristics (Refer to Figure 1-1 and Table 1-1 for pin configuration) All output signals can be tri-stated by driving STEN inactive The output buffers of the bi-directional data pins D15-D0 are also tri-state they only leave the floating state during read cycles when the Math CoProcessor is selected 4 1 1 Intel386 CPU CLOCK 2 (CPUCLK2) This input uses the CLK2 signal of the CPU to time the bus control logic Several other Math CoProcessor signals are referenced to the rising edge of this signal When CKM e 1 (synchronous mode) this pin Table 4-1 Pin Summary Pin Name Function Active State Execution Control CPUCLK2 NUMCLK2 CKM RESETIN Microprocessor Clock2 Math CoProcessor Clock2 Math CoProcessor Clock Mode System Reset I I I I Input Output Referenced To High CPUCLK2 Math CoProcessor Handshake PEREQ BUSY ERROR Processor Request Busy Status Error Status High Low Low Bus Interface D15-D0 WR ADS READY READYO Data Pins Write Read Bus Cycle Address Strobe Bus Ready Input Ready Output High Low Low Low Low Chip Port Select STEN NPS1 NPS2 CMD0 Status Enable Numerics Select Numerics Select Command 1 2 High Low High Low Power and Ground VCC VSS System Power System Ground I I I I CPUCLK2 CPUCLK2 CPUCLK2 CPUCLK2 IO I I I O CPUCLK2 CPUCLK2 CPUCLK2 CPUCLK2 CPUCLK2 O O O CPUCLK2 CPUCLK2 NUMCLK2 22 22 INTEL387 TM SX MATH COPROCESSOR 4 1 3 CLOCKING MODE (CKM) This pin is strapping option When it is strapped to VCC (HIGH) the Math CoProcessor operates in synchronous mode when strapped to VSS (LOW) the Math CoProcessor operates in asynchronous mode These modes relate to clocking of the internal data interface and control unit and the floating point unit only the bus control logic always operates synchronously with respect to the CPU Synchronous mode requires the use of only one clock the CPU's CLK2 Use of synchronous mode eliminates one clock generator from the board design and is recommended for all designs Synchronous mode also allows the internal Power Management Unit to enable the idle and standby power saving modes Asynchronous mode can provide higher performance of the floating point unit by running a faster clock on NUMCLK2 (The CPU's CLK2 must still be connected to CPUCLK2 input ) This allows the floating point unit to run up to 40% faster than in synchronous mode Internal power management is disabled in asynchronous mode 4 1 4 SYSTEM RESET (RESETIN) A LOW to HIGH transition on this pin causes the Math CoProcessor to terminate its present activity and to enter a dormant state RESETIN must remain active (HIGH) for at least 40 CPUCLK2 (NUMCLK2 if CKM e 0) periods The HIGH to LOW transitions of RESETIN must be synchronous with CPUCLK2 so that the phase of the internal clock of the bus control logic (which is the CPUCLK2 divided by two) is the same as the phase of the internal clock of the CPU After RESETIN goes LOW at least 50 CPUCLK2 (NUMCLK2 if CKM e 0) periods must pass before the first Math CoProcessor instruction is written into the Math CoProcessor This pin should be connected to the CPU RESET pin Table 4-2 shows the status of the output pins during the reset sequence After a reset all output pins return to their inactive state except for ERROR which remains active (for CPU recognition) until cleared Table 4-2 Output Pin Status during Reset Pin Value HIGH LOW Tri-State OFF Pin Name READYO BUSY PEREQ ERROR D15-D0 4 1 5 PROCESSOR REQUEST (PEREQ) When active this pin signals to the CPU that the Math CoProcessor is ready for data transfer to from its data FIFO When all data is written to or read from the data FIFO PEREQ is deactivated This signal always goes inactive before BUSY goes inactive This signal is reference to CPUCLK2 It should be connected to the CPU PEREQ input pin 4 1 6 BUSY STATUS (BUSY ) When active this pin signals to the CPU that the Math CoProcessor is currently executing an instruction This signal is referenced to CPUCLK2 It should be connected to the CPU BUSY input pin 4 1 7 ERROR STATUS (ERROR ) This pin reflects the ES bit of the status register When active it indicates that an unmasked exception has occurred This signal can be changed to the inactive state only by the following instructions (without a preceding WAIT) FNINIT FNCLEX FNSTENV FNSAVE FLDCW FLDENV and FRSTOR ERROR is driven active during RESET to indicate to the CPU that the Math CoProcessor is present This pin is referenced to NUMCLK2 (or CPUCLK2 if CKM e 1) It should be connected to the ERROR pin of the CPU 4 1 8 DATA PINS (D15 - D0) These bi-directional pins are used to transfer data and opcodes between the CPU and Math CoProcessor They are normally connected directly to the corresponding CPU data pins HIGH state indicates a value of one D0 is the least significant data bit Timings are referenced to rising edge of CPUCLK2 4 1 9 WRITE READ BUS CYCLE (W R ) This signal indicates to the Math CoProcessor whether the CPU bus cycle in progress is a read or a write cycle This pin should be connected directly to the CPU's W R pin HIGH indicates a write cycle to the Math CoProcessor LOW a read cycle from the Math CoProcessor This input is ignored if any of the signals STEN NPS1 or NPS2 are inactive Setup and hold times are referenced to CPUCLK2 4 1 10 ADDRESS STROBE (ADS ) This input in conjunction with the READY input indicates when the Math CoProcessor bus control logic may sample W R and the chip select signals Setup and hold times are referenced to CPUCLK2 This pin should be connected to the ADS pin of the CPU 23 23 INTEL387 TM SX MATH COPROCESSOR 4 1 11 BUS READY INPUT (READY ) This input indicates to the Math CoProcessor when a CPU bus cycle is to be terminated It is used by the bus control logic to trace bus activities Bus cycles can be extended indefinitely until terminated by READY This input should be connected to the same signal that drives the CPU's READY input Setup and hold times are referenced to CPUCLK2 4 1 12 READY OUTPUT (READYO ) This pin is activated at such a time that write cycles are terminated after two clocks (except FLDENV and FRSTOR) and read cycles after three clocks In configurations where no extra wait states are required this pin must directly or indirectly drive the READY input of the CPU Refer to the section entitled ``BUS OPERATION'' for details This pin is activated only during bus cycles that select the Math CoProcessor This signal is referenced to CPUCLK2 (FLDENV and FRSTOR require data transfers larger than the FIFO Therefore PEREQ is activated for the duration of transferring 2 words of 32 bits and then deactivated until the FIFO is ready to accept two additional words The length of the write cycles of the last operand word in each transfer as well as the first operand word transfer of the entire instruction is 3 clocks instead of 2 clocks This is done to give the Intel386 CPU enough time to sample PEREQ and to notice that the INTEL387 is not ready for additional transfers ) 4 1 13 STATUS ENABLE (STEN) This pin serves as a chip select for the Math CoProcessor When inactive this pin forces BUSY PEREQ ERROR and READYO outputs into a floating state D15-D0 are normally floating and will leave the floating state only if STEN is active and additional conditions are met (read cycle) STEN also causes the chip to recognize its other chip select inputs STEN makes it easier to do on-board testing (using the overdrive method) of other chips in systems containing the Math CoProcessor STEN should be pulled up with a resistor so that it can be pulled down when testing In boards that do not use on-board testing STEN should be connected to VCC Setup and hold times are relative to CPUCLK2 Note that STEN must maintain the same setup and hold times as NPS1 NPS2 and CMD0 (i e if STEN changes state during a Math CoProcessor bus cycle it must change state during the same CLK period as the NPS1 NPS2 and CMD0 signals) 4 1 14 MATH COPROCESSOR SELECT 1 (NPS1 ) When active (along with STEN and NPS2) in the first period of a CPU bus cycle this signal indicates that the purpose of the bus cycle is to communicate with the Math CoProcessor This pin should be connected directly to the M IO pin of the CPU so that the Math CoProcessor is selected only when the CPU performs I O cycles Setup and hold times are referenced to the rising edge of CPUCLK2 4 1 15 MATH COPROCESSOR SELECT 2 (NPS2) When active (along with STEN and NPS1 ) in the first period of a CPU bus cycle this signal indicates that the purpose of the bus cycle is to communicate with the Math CoProcessor This pin should be connected directly to the A23 pin of the CPU so that the Math CoProcessor is selected only when the CPU issues one of the I O addresses reserved for the Math CoProcessor (8000F8h 8000FCh or 8000FEh which is treated as 8000FCh by the Math CoProcessor) Setup and hold times are referenced to the rising edge of CPUCLK2 4 1 16 COMMAND (CMD0 ) During a write cycle this signal indicates whether an opcode (CMD0 active low) or data (CMD0 inactive high) is being sent to the Math CoProcessor During a read cycle it indicates whether the control or status register (CMD0 active) or a data register (CMD0 ) is being read CMD0 should be connected directly to the A2 output of the CPU Setup and hold times are referenced to the rising edge of CPUCLK2 at the end of PH2 4 1 17 SYSTEM POWER (VCC) System power provides the a 5V DC supply input All VCC pins should be tied together on the circuit board and local decoupling capacitors should be used between VCC and VSS 4 1 18 SYSTEM GROUND (VSS) System ground provides the 0V connection from which all inputs and outputs are measured All VSS pins should be tied together on the circuit board and local decoupling capacitors should be used between VCC and VSS 24 24 INTEL387 TM SX MATH COPROCESSOR 4 2 System Configuration The INTEL387 SX Math CoProcessor is designed to interface with the Intel386 SX Microprocessor as shown by Figure 4-1 A dedicated communication protocol makes possible high-speed transfer of opcodes and operands between the CPU and Math CoProcessor The INTEL387 SX Math CoProcessor is designed so that no additional components are required for interface with the CPU Most control pins of the Math CoProcessor are connected directly to pins of the CPU The interface between the Math CoProcessor and the CPU has these characteristics The CPU and Math CoProcessor share the same reset signals They may also share the same clock input however for greatest performance an external oscillator may be needed The corresponding Busy ERROR and PEREQ pins are connected together The Math CoProcessor NPS1 and NPS2 inputs are connected to the latched CPU M IO and A23 outputs respectively For Math CoProcessor cycles M IO is always LOW and A23 always HIGH to the latched A2 output The Intel386 SX Microprocessor generates address 8000F8H when writing a command and address 8000FCH or 8000FEH (treated as 8000FCH by the INTEL387 SX Math CoProcessor) when writing or reading data It does not generate any other addresses during Math CoProcessor bus cycles The Math CoProcessor input CMD0 is connected The Math CoProcessor shares the local bus of the Intel386 SX Microprocessor 240225 - 6 Figure 4-1 Intel386 TM SX CPU and INTEL387 TM SX Math CoProcessor System Configuration 25 25 INTEL387 TM SX MATH COPROCESSOR FIFO or the instruction decoder The instruction decoder decodes the ESC instructions sent to it by the CPU and generates controls that direct the data flow in the FIFO It also triggers the microinstruction sequencer that controls execution of each instruction If the ESC instruction is FINIT FCLEX FSTSW FSTSW AX FSTCW FSETPM or FRSTPM the control unit executes it independently of the FPU and the sequencer The data interface and control unit is the unit that generates the BUSY PEREQ and ERROR signals that synchronize the Math CoProcessor activities with the CPU 4 3 3 FLOATING POINT UNIT The FPU executes all instructions that involve the register stack including arithmetic logical transcendental constant and data transfer instructions The data path in the FPU is 84 bits wide (68 significant bits 15 exponent bits and a sign bit) which allows internal operand transfers to be performed at very high speeds 4 3 4 POWER MANAGEMENT UNIT The Power Management Unit (PMU) controls all internal power savings circuits When the Math CoProcessor is not executing an instruction the PMU disables the internal clock to the FPU Control Unit and Data Interface within three clocks The Bus Control Logic remains enabled to accept the next instruction Upon decode of a valid Math CoProcessor bus cycle the PMU enables the internal clock to all circuits No loss in performance occurs 4 3 Math CoProcessor Architecture As shown in Figure 2-1 Block Diagram the INTEL387 SX Math CoProcessor is internally divided into four sections the Bus Control Logic (BCL) the Data Interface and Control Logic the Floating Point Unit (FPU) and the Power Management Unit (PMU) The Bus Control Logic is responsible for the CPU bus tracking and interface The BCL is the only unit in the Math CoProcessor that must run synchronously with the CPU the rest of the Math CoProcessor can run asynchronously with respect to the CPU The Data Interface and Control Unit is responsible for the data flow to and from the FPU and the control registers for receiving the instructions decoding them sequencing the microinstructions and for handling some of the administrative instructions The Floating Point Unit (with the support of the control unit which contains the sequencer and other support units) executes the mathematical instructions The Power Manager is new to the INTEL387 family It is responsible for shutting down idle sections of the device to save power 4 3 1 BUS CONTROL LOGIC The BCL communicates solely with the CPU using I O bus cycles The BCL appears to the CPU as a special peripheral device It is special in two respects the CPU initiates I O automatically when it encounters ESC instructions and the CPU uses reserved I O addresses to communicate with the BCL The BCL does not communicate directly with memory The CPU performs all memory access transferring input operands from the memory to the Math CoProcessor and transferring outputs from the Math CoProcessor to memory 4 3 2 DATA INTERFACE AND CONTROL UNIT The data interface and control unit latches the data and subject to BCL control directs the data to the 4 4 Bus Cycles All bus cycles are initiated by the CPU The pins STEN NPS1 NPS2 CMD0 and W R identify bus cycles for the Math CoProcessor Table 4-3 defines the types of Math CoProcessor bus cycles Table 4-3 Bus Cycle Definition STEN NPS1 0 1 1 1 1 1 1 X 1 X 0 0 0 0 NPS2 CMD0 X X 0 1 1 1 1 X X X 0 0 1 1 WR X X X 0 1 0 1 Bus Cycle Type Math CoProcessor not selected and all outputs in floating state Math CoProcessor not selected Math CoProcessor not selected CW or SW read from Math CoProcessor Opcode write to Math CoProcessor Data read from Math CoProcessor Data write to Math CoProcessor 26 26 INTEL387 TM SX MATH COPROCESSOR value has already been written or read by the Math CoProcessor before the CPU reads or changes the value Once it has started to execute a numerics instruction and has transferred and operands from the CPU the Math CoProcessor can process the instruction in parallel with and independent of the host CPU When the Math CoProcessor detects an exception it asserts the ERROR signal which causes a CPU interrupt 4 4 3 SYNCHRONOUS ASYNCHRONOUS MODES The internal logic of the Math CoProcessor can operate either directly from the CPU clock (synchronous mode) or from a separate clock (asynchronous mode) The two configurations are distinguished by the CKM pin In either case the bus control logic (BCL) of the Math CoProcessor is synchronized with the CPU clock Use of asynchronous mode allows the BCL and the FPU section of the Math CoProcessor to run at different speeds In this case the ratio of the frequency of NUMCLK2 to the frequency of CPUCLK2 must lie within the range 10 16 to 14 10 Use of synchronous mode eliminates one clock generator from the board design The internal Power Management Unit of the INTEL387 SX Math CoProcessor is disabled in asynchronous mode 4 4 4 AUTOMATIC BUS CYCLE TERMINATION In configurations where no extra wait states are required READYO can drive the CPU's READY input and the Math CoProcessors READY input If wait states are required this pin should be connected to the logic that ORs all READY outputs from peripheral devices on the CPU bus READYO is asserted by the Math CoProcessor only during I O cycles that select the Math CoProcessor Refer to Section 5 0 Bus Operation for details 4 4 1 INTEL387 SX MATH COPROCESSOR ADDRESSING The NPS1 NPS2 and CMD0 signals allow the Math CoProcessor to identify which bus cycles are intended for the Math CoProcessor The Math CoProcessor responds to I O cycles when the I O address is 8000F8h 8000FCh and 8000FEh (treated as 8000FCh) The Math CoProcessor responds to I O cycles when bit 23 of the I O address is set In other words the Math CoProcessor acts as an I O device in a reserved I O address space Because A23 is used to select the INTEL387 SX Math CoProcessor for data transfers it is not possible for a program running on the CPU to address the Math CoProcessor with an I O instruction Only ESC instructions cause the CPU to communicate with the Math CoProcessor 4 4 2 CPU MATH COPROCESSOR SYNCHRONIZATION The pins BUSY PEREQ and ERROR are used for various aspects of synchronization between the CPU and the Math CoProcessor BUSY is used to synchronize instruction transfer from the CPU to the Math CoProcessor When the Math CoProcessor recognizes an ESC instruction it asserts BUSY For most ESC instructions the CPU waits for the Math CoProcessor to deassert BUSY before sending the new opcode The Math CoProcessor uses the PEREQ pin of the CPU to signal that the Math CoProcessor is ready for data transfer to or from its data FIFO The Math CoProcessor does not directly access memory rather the CPU provides memory access services for the Math CoProcessor (For this reason memory access on behalf of the Math CoProcessor always obeys the protection rules applicable to the current CPU mode ) Once the CPU initiates an Math CoProcessor instruction that has operands the CPU waits for PEREQ signals that indicate when the Math CoProcessor is ready for operand transfer Once all operands have been transferred (or if the instruction has no operands) the CPU continues program execution while the Math CoProcessor executes the ESC instruction In 8087 8087 systems WAIT instructions may be required to achieve synchronization of both commands and operands In the Intel386 Microprocessor and INTEL387 Math CoProcessor systems however WAIT instructions are required only for operand synchronization namely after Math CoProcessor stores to memory (except FSTSW and FSTCW) or load from memory (In 80286 80287 systems WAIT is required before FLDENV and FRSTOR ) Used this way WAIT ensures that the 50 BUS OPERATION With respect to bus interface the INTEL387 SX Math CoProcessor is fully synchronous with the CPU Both operate at the same rate because each generates its internal CLK signal by dividing CPUCLK2 by two Furthermore both internal CLK signals are in phase because they are synchronized by the same RESETIN signal A bus cycle for the Math CoProcessor starts when the CPU activates ADS and drives new values on the address and cycle definition lines (W R M IO etc ) The Math CoProcessor examines the address and cycle definition lines in the same CLK period during which ADS is activated This CLK period is considered the first CLK of the bus cycle 27 27 INTEL387 TM SX MATH COPROCESSOR During this first CLK period the Math CoProcessor also examines the W R input signal to determine whether the cycle is a read or a write cycle and examines the CMD0 input to determine whether an opcode operand or control status register transfer is to occur The INTEL387 SX Math CoProcessor supports both pipelined (i e overlapped) and non-pipelined bus cycles A non-pipelined cycle is one for which the CPU asserts ADS when no other bus cycle is in progress A pipelined bus cycle is one for which the CPU asserts ADS and provides valid next address and control signals before the prior Math CoProcessor cycle terminates The CPU may do this as early as the second CLK period after asserting ADS for the prior cycle Pipelining increases the availability of the bus by at least one CLK period The INTEL387 SX Math CoProcessor supports pipelined bus cycles in order to optimize address pipelining by the CPU for memory cycles Bus operation is described in terms of an abstract state machine Figure 5-1 illustrates the states and state transitions for Math CoProcessor bus cycles READYO output of the Math CoProcessor indicates when a Math CoProcessor bus cycle may be terminated if no extra wait states are required For all write cycles (except those for the instructions FLDENV and FRSTOR) READYO is always asserted during the first TRS state regardless of the number of wait states For all read cycles (and write cycles for FLDENV and FRSTOR) READY is always asserted in the second TRS state regardless of the number of wait states These rules apply to both pipelined and non-pipelined cycles Systems designers may use READYO in one of the following ways 1 Connect it (directly or through logic that ORs READY signals from other devices) to the READY inputs of the CPU and Math CoProcessor 2 Use it as one input to a wait-state generator The following sections illustrate different types of INTEL387 SX Math CoProcessor bus cycles Because different instructions have different amounts of overhead before between and after operand transfer cycles it is not possible to represent in a few diagrams all of the combinations of successive operand transfer cycles The following bus cycle diagrams show memory cycles between Math CoProcessor operand transfer cycles Note however that during FRSTOR some consecutive accesses to the Math CoProcessor do not have intervening memory accesses For the timing relationship between operand transfer cycles and opcode write or other overhead activities see Figure 7-7 ``Other Parameters'' TI is the idle state This is the state of the bus logic after RESET the state to which bus logic returns after every non-pipelined bus cycle and the state to which bus logic returns after a series of pipelined cycles TRS is the READY sensitive state Different types of bus cycles may require a minimum of one or two successive TRS states The bus logic remains in TRS state until READY is sensed at which point the bus cycle terminates Any number of wait states may be implemented by delaying READY thereby causing additional successive TRS states 5 1 Non-Pipelined Bus Cycles Figure 5-2 illustrates bus activity for consecutive non-pipelined bus cycles At the second clock of the bus cycle the Math CoProcessor enters the TRS state During this state it samples the READY input and stays in this state as long as READY is inactive 5 1 1 WRITE CYCLE In write cycles the Math CoProcessor drives the READYO signal for one CLK period during the second CLK period of the cycle (i e the first TRS state) therefore the fastest write cycle takes two CLK periods (see cycle 2 of Figure 5-2) For the instructions FLDENV and FRSTOR however the Math CoProcessor forces wait state by delaying the activation of READYO to the second TRS state (not shown in Figure 5-2) The Math CoProcessor samples the D15 - D0 inputs into data latches at the falling edge of CLK as long as it stays in TRS state TP is the first state for every pipelined bus cycle This state is not used by non-pipelined cycles Note that the bus logic tracks bus state regardless of the values on the chip port select pins The 240225 - 7 Figure 5-1 Bus State Diagram 28 28 INTEL387 TM SX MATH COPROCESSOR 240225 - 8 Cycles 1 2 represent part of the operand transfer cycle for instructions involving either 4-byte or 8-byte operand loads Cycles 3 4 represent part of the operand transfer cycle for a store operation Cycles 1 2 could repeat here or TI states for various non-operand transfer cycles and overhead Figure 5-2 Non-Pipelined Read and Write Cycles When READY is asserted the Math CoProcessor returns to the idle state Simultaneously with the Math CoProcessor entering the idle state the CPU may assert ADS again signaling the beginning of yet another cycle 5 1 2 READ CYCLE At the rising edge of CLK in the second CLK period of the cycle (i e the first TRS state) the Math CoProcessor starts to drive the D15-D0 outputs and continues to drive them as long as it stays in TRS state At least one wait state must be inserted to ensure that the CPU latches the correct data Because the Math CoProcessor starts driving the data bus only at the rising edge of CLK in the second clock period of the bus cycle not enough time is left for the data signals to propagate and be latched by the CPU before the next falling edge of CLK Therefore the Math CoProcessor does not drive the READYO signal until the third CLK period of the cycle Thus if the READYO output drives the CPU's READY input one wait state is automatically inserted Because one wait state is required for Math CoProcessor reads the minimum length of a Math CoProcessor read cycle is three CLK periods as cycle 3 of Figure 5-2 shows When READY is asserted the Math CoProcessor returns to the idle state Simultaneously with the Math CoProcessor's entering the idle state the CPU may assert ADS again signaling the beginning of yet another cycle The transition from TRS state to idle state causes the Math CoProcessor to put the D15 - D0 outputs into the floating state allowing another device to drive the data bus 5 2 Pipelined Bus Cycles Because all the activities of the Math CoProcessor bus interface occur either during the TRS state or 29 29 INTEL387 TM SX MATH COPROCESSOR during the transitions to or from that state the only difference between a pipelined and a non-pipelined cycle is the manner of changing from one state to another The exact activities during each state are detailed in the previous section ``Non-pipelined Bus Cycles'' When the CPU asserts ADS before the end of a bus cycle both ADS and READY are active during a TRS state This condition causes the Math CoProcessor to change to a different state named TP One clock period after a TP state the Math CoProcessor always returns to the TRS state In consecutive pipelined cycles the Math CoProcessor bus logic uses only the TRS and TP states Figure 5-3 shows the fastest transitions into and out of the pipelined bus cycles Cycle 1 in the figure represents a non-pipelined cycle (Non-pipelined write are always followed by another non-pipelined cycle because READY is asserted before the earliest possible assertion of ADS for the next cycle ) Figure 5-4 shows pipelined write and read cycles with one additional TRS state beyond the minimum required To delay the assertion of READY requires external logic 5 3 Mixed Bus Cycles When the Math CoProcessor bus logic is in the TRS state it distinguishes between non-pipelined and pipelined cycles according to the behavior of ADS and READY In a non-pipelined cycle only READY is activated and the transition is from the TRS state to the idle state In a pipelined cycle both READY and ADS are active and the transition is first from TRS state to TP state then after one clock period back to TRS state 240225 - 9 Cycle 1 - Cycle 4 represent the operand transfer cycle for an instruction involving a transfer of two 32-bit loads in total The opcode write cycles and other overhead are not shown Note that the next cycle will be a pipelined cycle if both READY and ADS are sampled active at the end of a TRS state of the current cycle Figure 5-3 Fastest Transitions to and from Pipelined Cycles 30 30 INTEL387 TM SX MATH COPROCESSOR 240225 - 10 NOTE 1 Cycles between operand write to the Math CoProcessor and storing result Figure 5-4 Pipelined Cycles with Wait States 31 31 INTEL387 TM SX MATH COPROCESSOR tion upon completion of the instruction PEREQ is activated within this interval If ERROR is ever asserted it would be asserted at least six CPUCLK2 periods after the deactivation of PEREQ and would be deasserted at least six CPUCLK2 periods before the deactivation of BUSY 5 4 BUSY and PEREQ Timing Relationship Figure 5-5 shows the activation of BUSY at the beginning of instruction execution and its deactiva- 240225 - 11 NOTES 1 Instruction dependent 2 PEREQ is an asynchronous input to the Intel386 TM Microprocessor it may not be asserted (instruction dependent) 3 More operand transfers 4 Memory read (operand) cycle is not shown Figure 5-5 STEN BUSY and PEREQ Timing Relationships 32 32 INTEL387 TM SX MATH COPROCESSOR The ambient temperature (TA) is guaranteed as long as TC is not violated The ambient temperature can be calculated from the iJC (thermal resistance constant from the transistor junction to the case) and iJA (thermal resistance from junction to ambient) from the following calculations Junction Temperature TJ e TC a P iJC Ambient Temperature TA e TJ b P iJA Case Temperature TC e TA a P (iJA b iJC) Values for iJA and iJC are given in Table 6-1 for the 68 pin PLCC package iJC is given at various airflows Table 6-2 shows the maximum TA allowable without exceeding TC at various airflows Note that TA can be improved further by attaching a heat sink to the package P is calculated by using the maximum hot ICC and maximum VCC 60 PACKAGE SPECIFICATIONS 6 1 Mechanical Specifications The INTEL387 SX Math CoProcessor is packaged in a 68-pin PLCC package Detailed mechanical specifications can be found in the Intel Packaging Specification Order Number 231369 6 2 Thermal Specifications The INTEL387 SX Math CoProcessor is specified for operation when the case temperature is within the range of 0 C to 100 C The case temperature (TC) may be measured in any environment to determine whether the INTEL387 SX Math CoProcessor is within the specified operating range The case temperature should be measured at the center of the top surface Table 6-1 Thermal Resistances ( C Watt) iJC and iJA iJA versus Airflow - ft min (m sec) Package 68-Pin PLCC iJC 8 0 (0) 30 200 (1 01) 25 400 (2 03) 20 600 (3 04) 15 5 800 (4 06) 13 1000 (5 07) 12 Table 6-2 Maximum TA at Various Airflows TA ( C) versus Airflow - ft min (m sec) Package 68-Pin PLCC 0 (0) 84 9 200 (1 01) 88 3 400 (2 03) 91 8 600 (3 04) 94 8 800 (4 06) 96 6 1000 (5 07) 97 2 Maximum TA is calculated at maximum VCC and maximum ICC 70 ELECTRICAL CHARACTERISTICS The following specifications represent the targets of the design effort They are subject to change without notice Contact your Intel representative to get the most up-to-date values 7 1 Absolute Maximum Ratings Case Temperature TC Under Bias 0 C to a 100 C b 65 C to a 150 C Storage Temperature Voltage on Any Pin b 0 5 to VCC a 0 5 with Respect to Ground Power Dissipation 0 8W NOTICE This is a production data sheet The specifications are subject to change without notice WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability 33 33 INTEL387 TM SX MATH COPROCESSOR 7 2 D C Characteristics Table 7-1 D C Specifications TC e 0 C to a 100 C VCC e 5V g10% Symbol VIL VIH VCL VCH VOL VOH VOH ICC Parameter Input LO Voltage Input HI Voltage CPUCLK2 and NUMCLK2 Input LO Voltage CPUCLK2 and NUMCLK2 Input HI Voltage Output LO Voltage Output HI Voltage Output HI Voltage Power Supply Current Dynamic Mode Freq e 33 MHz(5) Freq e 25 MHz(5) Freq e 20 MHz(5) Freq e 16 MHz(5) Freq e 1 MHz(5) Idle Mode(6) Input Leakage Current I O Leakage Current Input Capacitance I O Capacitance Clock Capacitance 7 7 7 Min b0 3 Max a0 8 VCC a 0 3 a0 8 Units V V V V V V V Test Conditions (Note 1) (Note 1) 20 b0 3 VCC b 0 8 24 VCC b 0 8 VCC a 0 8 0 45 (Note 2) (Note 3) (Note 4) 150 150 125 100 20 7 g15 g15 mA mA mA mA mA mA mA mA pF pF pF ICC typ ICC typ ICC typ ICC typ ICC typ ICC typ e e e e e e 135 mA 130 mA 110 mA 90 mA 5 mA 4 mA ILI ILO CIN CO CCLK 0V s VIN s VCC 0 45V s VO s VCC fc e 1 MHz fc e 1 MHz fc e 1 MHz 10 12 20 NOTES 1 This parameter is for all inputs excluding the clock inputs 2 This parameter is measured at IOL as follows Data e 4 0 mA READYO ERROR BUSY PEREQ e 25 mA 3 This parameter is measured at IOH as follows Data e 1 0 mA READYO ERROR BUSY PEREQ e 0 6 mA 4 This parameter is measured at IOH as follows Data e 0 2 mA READYO ERROR BUSY PEREQ e 0 12 mA 5 Synchronous Clock Mode (CKM e 1) ICC is measured at steady state maximum capacitive loading on the outputs and worst-case D C level at the inputs 6 INTEL387 SX Math CoProcessor Internal Idle Mode Synchronous clock mode clock and control inputs are active but the Math CoProcessor is not executing an instruction Outputs driving CMOS inputs 34 34 INTEL387 TM SX MATH COPROCESSOR 7 3 A C Characteristics Table 7-2a Timing Requirements of the Bus Interface Unit TC e 0 C to a 100 C VCC e 5V g10% (All measurements made at 1 5V unless otherwise specified) 16 MHz - 25 MHz Min (ns) 20 6 3 6 4 Max (ns) DC 33 MHz Min (ns) 15 6 25 45 6 25 45 Max (ns) DC Test Conditions 2 0V 2 0V VCC b 0 8V 2 0V 0 8V From VCC b 0 8V to 0 8V From 0 8V to VCC b 0 8V CL CL CL CL e e e e Pin Symbol Parameter Refer to Figure 72 CPUCLK2 CPUCLK2 CPUCLK2 CPUCLK2 CPUCLK2 CPUCLK2 CPUCLK2 READYO PEREQ BUSY ERROR D15-D0 D15-D0 D15-D0 D15-D0 READYO PEREQ BUSY ERROR ADS ADS WR WR READY READY CMD0 CMD0 NPS1 NPS2 NPS1 NPS2 STEN STEN RESETIN RESETIN t1 t2a t2b t3a t3b t4 t5 t7a t7b t7c t7d t8 t10 t11 t12 t13a t13b t13c t13d t14a t15a t14b t15b t16a t17a t16b t17b t16c t17c t16d t17d t18 t19 Period High Time High Time Low Time Low Time Fall Time Rise Time Out Delay Out Delay Out Delay Out Delay Out Delay Setup Time Hold Time Float Time Float Time Float Time Float Time Float Time Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time 7 7 4 4 4 4 1 11 11 6 1 1 1 1 15 4 15 4 9 4 16 2 16 2 15 2 8 3 25 23 23 23 45 4 4 4 4 0 8 8 6 1 1 1 1 13 4 13 4 7 4 13 2 13 2 13 2 5 2 4 4 17 21 21 23 37 50 pF 50 pF 50 pF 50 pF 73 CL e 50 pF 74 24 40 40 40 40 19 30 30 30 30 76 74 74 75 NOTE Float condition occurs when maximum output current becomes less than ILO in magnitude Float delay is not tested 35 35 INTEL387 TM SX MATH COPROCESSOR Table 7-2b Timing Requirements of the Execution Unit (Asynchronous Mode CKM e 0) 16 MHz - 25 MHz Min (ns) 20 6 3 6 4 Max (ns) 500 33 MHz Min (ns) 15 6 25 45 6 25 45 Max (ns) 500 Test Conditions 2 0V 2 0V VCC b 0 8V 2 0V 0 8V From VCC b 0 8V to 0 8V From 0 8V to VCC b 0 8V Refer to Figure 72 Pin Symbol Parameter NUMCLK2 NUMCLK2 NUMCLK2 NUMCLK2 NUMCLK2 NUMCLK2 NUMCLK2 NUMCLK2 CPUCLK2 t1 t2a t2b t3a t3b t4 t5 Period High Time High Time Low Time Low Time Fall Time Rise Time Ratio 7 7 10 16 14 10 10 16 6 6 14 10 NOTE If not used (CKM e 1) tie NUMCLK2 low Table 7-2c Other A C Parameters Pin RESETIN RESETIN BUSY BUSY ERROR Symbol t30 t31 t32 t33 t34 t35 t36 Parameter Duration RESETIN Inactive to 1st Opcode Write Duration ERROR (In)Active to BUSY Inactive PEREQ Inactive to ERROR Active READY Active Active to BUSY Min 40 50 6 6 6 0 4 4 Max Units NUMCLK2 NUMCLK2 CPUCLK2 CPUCLK2 CPUCLK2 CPUCLK2 CPUCLK2 PEREQ ERROR READY READY BUSY Minimum Time from Opcode Write to Opcode Operand Write Minimum Time from Operand Write to Operand Write READY t37 4 CPUCLK2 36 36 INTEL387 TM SX MATH COPROCESSOR 240225 - 12 NOTE Typical part under worst-case conditions Figure 7-1a Typical Output Valid Delay vs Load Capacitance at Max Operating Temperature 240225 - 13 240225 - 14 NOTE Typical part under worst-case conditions Figure 7-1b Typical Output Slew Time vs Load Capacitance at Max Operating Temperature 240225 - 15 Figure 7-1c Maximum ICC vs Frequency 37 37 INTEL387 TM SX MATH COPROCESSOR 240225 - 16 Figure 7-2 CPUCLK2 NUMCLK2 Waveform and Measurement Points for Input Output 240225 - 17 Figure 7-3 Output Signals 38 38 INTEL387 TM SX MATH COPROCESSOR 240225 - 18 Figure 7-4 Input and I O Signals 240225 - 19 NOTE The second internal processor phase following RESET high to low transition is PH2 Figure 7-5 RESET Signal 39 39 INTEL387 TM SX MATH COPROCESSOR 240225 - 20 Figure 7-6 Float from STEN 240225 - 21 In NUMCLK2's or last operand NOTE 1 Memory read (operand) cycle is not shown Figure 7-7 Other Parameters 40 40 INTEL387 TM SX MATH COPROCESSOR grammer's Reference Manual for the CPU) SIB (Scale Index Base) byte and DISP (displacement) are optionally present in instructions that have MOD and R M fields Their presence depends on the values of MOD and R M as for instructions of the CPU The instruction summaries that follow in Table 8-2 assume that the instruction has been prefetched decoded and is ready for execution that bus cycles do not require wait states that there are no local bus HOLD requests delaying processor access to the bus and that no exceptions are detected during instruction execution If the instruction has MOD and R M fields that call for both base and index registers add one clock 80 INTEL387 SX MATH COPROCESSOR INSTRUCTION SET Instructions for the INTEL387 SX Math CoProcessor assume one of the five forms shown in Table 8-1 In all cases instructions are at least two bytes long and begin with the bit pattern 11011B which identifies the ESCAPE class of instruction Instructions that refer to memory operands specify addresses using the CPU's addressing modes MOD (Mode field) and R M (Register Memory specifier) have the same interpretation as the corresponding fields of CPU instructions (refer to Pro- Table 8-1 Instruction Formats Instruction First Byte 1 2 3 4 5 11011 11011 11011 11011 11011 15 -11 d 0 0 10 OPA MF P 0 1 9 1 OPA OPA 1 1 8 1 1 1 7 MOD MOD 1 1 1 6 1 1 5 Second Byte 1 OPB OPB OPB OP OP 43210 RM RM ST(i) Optional Fields SIB SIB DISP DISP OP e Instruction opcode possibly split into two fields OPA and OPB MF e Memory Format 00 - 32-bit real 01 - 32-bit integer 10 - 64-bit real 11 - 16-bit integer d e Destination 0 - Destination is ST(0) 1 - Destination is ST(i) R XOR d e 0 - Destination (op) Source R XOR d e 1 - Source (op) Destination In FSUB and FDIV the low-order bit of OPB is the R (reversed) bit P e POP 0 - Do not pop stack 1 - Pop stack after operation ESC e 11011 ST(i) e Register stack element i 000 e Stack top 001 e Second stack element 111 e Eighth stack element 41 41 INTEL387 TM SX MATH COPROCESSOR Encoding Instruction DATA TRANSFER FLD e Loada Integer real memory to ST(0) Long integer memory to ST(0) Extended real memory to ST(0) BCD memory to ST(0) ST(i) to ST(0) FST e Store ST(0) to integer real memory ST(0) to ST(i) FSTP e Store and Pop ST(0) to integer real memory ST(0) to long integer memory ST(0) to extended real memory ST(0) to BCD memory ST(0) to ST(i) FXCH e Exchange ST(i) and ST(0) COMPARISON FCOM e Compare Integer real memory to ST(0) ST(i) to ST(0) FCOMP e Compare and pop Integer real memory to ST(0) ST(i) to ST(0) FCOMPP e Compare and pop twice ST(1) to ST(0) FTST e Test ST(0) FUCOM e Unordered compare FUCOMP e Unordered compare and pop FUCOMPP e Unordered compare and pop twice FXAM e Examine ST(0) ESC 101 11101 ST(i) ESC 110 ESC 001 ESC 101 1101 1001 1110 0100 11100 ST(i) ESC MF 0 ESC 000 MOD 011 R M 11011 ST(i) SIB DISP 15 - 27 ESC MF 0 ESC 000 MOD 010 R M 11010 ST(i) SIB DISP 15 - 27 ESC 001 11001 ST(i) ESC MF 1 ESC 111 ESC 011 ESC 111 ESC 101 MOD 011 R M MOD 111 R M MOD 111 R M MOD 110 R M 11011 ST (i) SIB DISP SIB DISP SIB DISP SIB DISP 27 - 45 ESC MF 1 ESC 101 MOD 010 R M 11010 ST(i) SIB DISP 27 - 45 Byte 0 Byte 1 Optional Bytes 2 - 6 32-Bit Real Clock Count Range 32-Bit 64-Bit Integer Real 16-Bit Integer ESC MF 1 ESC 111 ESC 011 ESC 111 ESC 001 MOD 000 R M MOD 101 R M MOD 101 R M MOD 100 R M 11000 ST(i) SIB DISP SIB DISP SIB DISP SIB DISP 11 - 20 28 - 44 20 - 27 42 - 53 30 - 58 16 - 47 49 - 101 7 - 12 59 - 78 7 - 11 59 58 - 76 59 - 78 64 - 86 50 - 56 59 58 - 76 116 - 194 7 - 11 10 - 17 36 - 54 18 - 31 39 - 62 13 - 21 36 - 54 18 - 31 39 - 62 13 - 21 13 - 21 17 - 25 13 - 21 13 - 21 ESC 010 ESC 001 1110 1001 1110 0101 13 - 21 24-37 Shaded areas indicate instructions not available in 8087 80287 NOTE a When loading single or double precision zero from memory add 5 clocks 42 42 INTEL387 TM SX MATH COPROCESSOR Encoding Instruction ARITHMETIC FADD e Add Integer real memory to ST(0) ST(i) and ST(0) FSUB e Subtract Integer real memory with ST(0) ST(i) to ST(0) FMUL e Multiply Integer real memory with ST(0) ST(i) and ST(0) FDIV e Divide Integer real memory with ST(0) ST(i) and ST(0) FSQRT i e Square root FSCALE e Scale ST(0) by ST(1) FPREM e Partial remainder FPREM1 e Partial remainder (IEEE) FRNDINT e Round ST(0) to integer FXTRACT e Extract components of ST(0) FABS e Absolute value of ST(0) FCHS e Change sign of ST(0) TRANSCENDENTAL FCOSk e Cosine of ST(0) FPTANk e Partial tangent of ST(0) FPATAN e Partial arctangent of ST(0) FSINk e Sine of ST(0) FSINCOSk e Sine and cosine of ST(0) F2XM1l e 2ST(0) b 1 FYL2Xm e ST(1) FYL2XP1n e ST(1) log2ST(0) log2 ST(0) a 1 0 ESC 001 ESC 001 ESC 001 ESC 001 ESC 001 ESC 001 ESC 001 ESC 001 1111 1111 1111 0010 1111 0011 1111 1110 1111 1011 1111 0000 1111 0001 1111 1001 ESC MF 0 ESC d P 0 ESC 001 ESC 001 ESC 001 ESC 001 ESC 001 MOD 11 R R M 1111 R R M 1111 1010 1111 1101 1111 1000 1111 0101 1111 1100 SIB DISP 79 - 87 ESC MF 0 ESC d P 0 MOD 001 R M 1100 1 R M SIB DISP 21 - 33 ESC MF 0 ESC d P 0 MOD 10 R R M 1110 R R M SIB DISP 14 - 31 ESC MF 0 ESC d P 0 MOD 000 R M 11000 ST(i) SIB DISP SIB DISP 14 - 31 Byte 0 Byte 1 Optional Bytes 2 - 6 32-Bit Real Clock Count Range 32-Bit Integer 64-Bit Real 16-Bit Integer 36 - 58 19 - 38 38 - 64 12 - 26b 36 - 58 19 - 38 38 - 64c 12 - 26d 45 - 73 27 - 57 46 - 74 17 - 50e 103 - 116f 85 - 95 105 - 124g 77 - 80h 97 - 111 44 - 82 56 - 140 81 - 168 41 - 62 ESC 001 ESC 001 ESC 001 1111 0100 1110 0001 1110 0000 42 - 63 14 - 21 17 - 24 122 - 680 162 - 430j 250 - 420 121 - 680 150 - 650 167 - 410 99 - 436 210 - 447 Shaded areas indicate instructions not available in 8087 80287 NOTES b Add 3 clocks to the range when d e 1 c Add 1 clock to each range when R e 1 d Add 3 clocks to the range when d e 0 e typical e 52 (When d e 0 46-54 typical e 49) f Add 1 clock to the range when R e 1 g 135 - 141 when R e 1 h Add 3 clocks to the range when d e 1 i b0 s ST(0) s a % j These timings hold for operands in the range lxl k q For operands not in this range up to 76 additional clocks may be needed to reduce the operand k 0 s ST(0) k 263 l b1 0 s ST(0) s 1 0 m 0 s ST(0) k % b% k ST(1) k a % n 0 s lST(0)l k 2-SQRT(2) 2 b% kST(1) k a % 43 43 INTEL387 TM SX MATH COPROCESSOR Encoding Instruction Byte 0 Byte 1 Optional Bytes 2 - 6 32-Bit Real Clock Count Range 32-Bit Integer 64-Bit Real 16-Bit Integer CONSTANTS FLDZ e Load a 0 0 to ST(0) FLD1 e Load a 1 0 to ST(0) FLDPI e Load q to ST(0) FLDL2T e Load log2(10) to ST(0) FLDL2E e Load log2(e) to ST(0) FLDLG2 e Load log10(2) to ST(0) FLDLN2 e Load loge(2) to ST(0) PROCESSOR CONTROL FINIT e Initialize Math CoProcessor FLDCW e Load control word from memory FSTCW e Store control word to memory FSTSW e Store status word to memory FSTSW AX e Store status word to AX FCLEX e Clear exceptions FSTENV e Store environment FLDENV e Load environment FSAVE e Save state FRSTOR e Restore state FINCSTP e Increment stack pointer FDECSTP e Decrement stack pointer FFREE e Free ST(i) FNOP e No operations ESC 011 ESC 001 ESC 001 ESC 101 ESC 111 ESC 011 ESC 001 ESC 001 ESC 101 ESC 101 ESC 001 ESC 001 ESC 101 ESC 001 1110 0011 MOD 101 R M MOD 111 R M MOD 111 R M 1110 0000 1110 0010 MOD 110 R M MOD 100 R M MOD 110 R M MOD 100 R M 1111 0111 1111 0110 1100 0 ST(i) 1101 0000 SIB DISP SIB DISP SIB DISP SIB DISP SIB DISP SIB DISP SIB DISP 33 19 15 15 13 11 117 - 118 85 402 - 403 415 21 22 18 12 ESC 001 ESC 001 ESC 001 ESC 001 ESC 001 ESC 001 ESC 001 1110 1110 1110 1000 1110 1011 1110 1001 1110 1010 1110 1100 1110 1101 10 - 17 15 - 22 26 - 36 26 - 36 26 - 36 25 - 35 26 - 38 44 44 INTEL387 TM SX MATH COPROCESSOR APPENDIX A INTEL387 SX MATH COPROCESSOR COMPATIBILITY A 1 8087 80287 Compatibility This section summarizes the differences between the INTEL387 SX Math CoProcessor and the 80287 Math CoProcessor Any migration from the 8087 directly to the INTEL387 SX Math CoProcessor must also take into account the differences between the 8087 and the 80287 Math CoProcessor as listed in Appendix B Many changes have been designed into the INTEL387 SX Math CoProcessor to directly support the IEEE standard in hardware These changes result in increased performance by eliminating the need for software that supports the standard A 1 1 GENERAL DIFFERENCES The INTEL387 SX Math CoProcessor supports only affine closure for infinity arithmetic not projective closure Operands for FSCALE and FPATAN are no longer restricted in range (except for g % ) F2XM1 and FPTAN accept a wider range of operands Rounding control is in effect for FLD constant Software cannot change entries of the tag word to values (other than empty) that differ from actual register contents After reset FINIT and incomplete FPREM the INTEL387 SX Math CoProcessor resets to zero the condition code bits C3 -C0 of the status word In conformance with the IEEE standard the INTEL387 SX Math CoProcessor does not support the special data formats pseudo-zero pseudo-NaN pseudo-infinity and unnormal The denormal exception has a different purpose on the INTEL387 SX Math CoProcessor A system that uses the denormal exception handler solely to normalize the denormal operands would better mask the denormal exception on the INTEL387 SX Math CoProcessor The INTEL387 SX Math CoProcessor automatically normalizes denormal operands when the denormal exception is masked A-1 45 INTEL387 TM SX MATH COPROCESSOR A 1 2 EXCEPTIONS A number of differences exist due to changes in the IEEE standard and to functional improvements to the architecture of the INTEL387 SX Math CoProcessor 1 When the overflow or underflow exception is masked the INTEL387 SX Math CoProcessor differs from the 80287 in rounding when overflow or underflow occurs The INTEL387 SX Math CoProcessor produces results that are consistent with the rounding mode 2 When the underflow exception is masked the INTEL387 SX Math CoProcessor sets its underflow flag only if there is also a loss of accuracy during denormalization 3 Fewer invalid-operations exceptions due to denormal operand because the instructions FSQRT FDIV FPREM and conversions to BCD or to integer normalize denormal operands before proceeding 4 The FSQRT FBSTP and FPREM instructions may cause underflow because they support denormal operands 5 The denormal exception can occur during the transcendental instruction and the FXTRACT instruction 6 The denormal exception no longer takes precedence over all other exceptions 7 When the denormal exception is masked the INTEL387 SX Math CoProcessor automatically normalizes denormal operands The 8087 80287 performs unnormal arithmetic which might produce an unnormal result 8 When the operand is zero the FXTRACT instruction reports a zero-divide exception and leaves b % in ST(1) 9 The status word has a new bit (SF) that signals when invalid-operation exceptions are due to stack underflow or overflow 10 FLD extended precision no longer reports denormal exceptions because the instruction is not numeric 11 FLD single double precision when the operand is denormal converts the number to extended precision and signals the denormal operand exception When loading a signaling NaN FLD single double precision signals an invalid-operation exception 12 The INTEL387 SX Math CoProcessor only generates quiet NaNs (as on the 80287) however the INTEL387 SX Math CoProcessor distinguishes between quiet NaNs and signaling NaNs Signaling NaNs trigger exceptions when they are used as operands quiet NaNs do not (except for FCOM FIST and FBSTP which also raise IE for quiet NaNs) 13 When stack overflow occurs during FPTAN and overflow is masked both ST(0) and ST(1) contain quiet NaNs The 80287 8087 leaves the original operand in ST(1) intact 14 When the scaling factor is g % the FSCALE instruction behaves as follows FSCALE (0 % ) generates the invalid operation exception FSCALE (finite b % ) generates zero with the same sign as the scaled operand FSCALE (finite a % ) generates % with the same sign as the scaled operand The 8087 80287 returns zero in the first case and raises the invalid-operation exception in the other cases 15 The INTEL387 SX Math CoProcessor returns signed infinity zero as the unmasked response to massive overflow underflow The 8087 and 80287 support a limited range for the scaling factor within this range either massive overflow underflow do not occur or undefined results are produced A-2 46 INTEL387 TM SX MATH COPROCESSOR APPENDIX B COMPATIBILITY BETWEEN THE 80287 AND 8087 MATH COPROCESSOR The 80286 80287 operating in Real Address mode will execute 8086 8087 programs without major modification However because of differences in the handling of numeric exceptions by the 80287 Math CoProcessor and the 8087 Math CoProcessor exception handling routines may need to be changed This appendix summarizes the differences between the 80287 Math CoProcessor and the 8087 Math CoProcessor and provides details showing how 8087 8087 programs can be ported to the 80286 80287 1 The Math CoProcessor signals exceptions through a dedicated ERROR line to the 80286 The Math CoProcessor error signal does not pass through an interrupt controller (the 8087 INT signal does) Therefore any interrupt controller oriented instructions in numeric exception handlers for the 8086 8087 should be deleted 2 The 8087 instructions FENI and FDISI perform no useful function in the 80287 If the 80287 encounters one of these opcodes in its instruction stream the instruction will effectively be ignored none of the 80287 internal states will be updated While 8086 8087 programs containing the instruction may be executed on the 80286 80287 it is unlikely that the exception handling routines containing these instructions will be completely portable to the 80287 3 Interrupt vector 16 must point to the numeric exception handling routine 4 The ESC instruction address saved in the 80287 includes any leading prefixes before the ESC opcode The corresponding address saved in the 8087 does not include leading prefixes 5 In Protected Address mode the format of the 80287's saved instruction and address pointers is different than for the 8087 The instruction opcode is not saved in Protected mode exception handlers will have to retrieve the opcode from memory if needed 6 Interrupt 7 will occur in the 80286 when executing ESC instructions with either TS (task switched) or EM (emulation) of the 80286 MSW set (TS e 1 or EM e 1) It TS is set then a WAIT instruction will also cause interrupt 7 An exception handler should be included in 80286 80287 code to handle these situations 7 Interrupt 9 will occur if the second or subsequent words of a floating point operand fall outside a segment's size Interrupt 13 will occur if the starting address of a numeric operand falls outside a segment's size An exception handler should be included in 80286 80287 code to report these programming errors 8 Except for the processor control instructions all of the 80287 numeric instructions are automatically synchronized by the 80286 CPU the 80286 CPU automatically tests the BUSY line from the 80287 to ensure that the 80287 has completed its previous instruction before executing the next ESC instruction No explicit WAIT instructions are required to assure this synchronization For the 8087 used witth 8086 and 8088 processors explicit WAITs are required before each numeric instruction to ensure synchronization Although 8086 8087 programs having explicit WAIT instructions will execute perfectly on the 80286 80287 without reassembly these WAIT instructions are unnecessary 9 Since the 80287 does not require WAIT instructions before each numeric instruction the ASM286 assembler does not automatically generate these WAIT instuctions The ASM86 assembler however automatically precedes every ESC instruction with a WAIT instruction Although numeric routines generated using the ASM86 assembler will generally execute correctly on the 80286 80287 reassembly using ASM286 may result in a more compact code image The processor control instructions for the 80287 may be coded using either a WAIT or No-WAIT form of mnemonic The WAIT forms of these instructions cause ASM286 to precede the ESC instructions with a CPU WAIT instruction in the identical manner as does ASM86 B-1 47 |
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